This invention relates to loop circuitry. More particularly, this invention relates to providing a variable-bandwidth loop filter in loop circuitry.
Integrated circuit (“ICs”) often require relatively accurate high-speed clock signals to facilitate synchronized operation. One way of providing relatively accurate clock signals is to provide phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry on the IC. Although the discussion herein focuses mainly on PLL circuitry, it will be noted that concepts of the invention could also be extended to DLL circuitry without deviating from the spirit or scope of the invention. As used herein, ICs can include programmable logic devices (“PLDs”), application-specific integrated circuits (“ASICs”), or circuits having characteristics of both PLDs and ASICs.
A basic PLL can include a phase-frequency detector (“PFD”), a charge pump, a loop filter, and a voltage-controlled oscillator (“VCO”) connected in series. An input reference signal can be fed to one input of the PFD. The output clock signal of the VCO, which can serve as the output signal of the PLL, can also be fed back to a second input of the PFD. If the feedback clock signal is not locked to the reference signal, then the PFD can output a signal whose voltage polarity is indicative of whether the feedback clock signal leads or lags the reference signal. Furthermore, the magnitude of that signal can be indicative of the amount of the lead or lag. That signal can be filtered by the charge pump and loop filter and input to the VCO, causing the frequency and phase of the output clock signal to change.
Under such operation, the output clock signal can eventually lock to the phase of the reference signal. In this simple example, the output signal can also lock to the frequency of the input reference signal, but in most PLLs, counters/dividers on the input and output of the PLL can be used to divide the frequency of the output clock signal, while a counter/divider in the feedback loop can be used to multiply the frequency of the output clock signal. Thus, the frequency of the output clock signal can often be a rational multiple of the frequency of the input reference signal.
The operation of a DLL can be similar to that of a PLL. A basic DLL can include a phase detector (“PD”), a charge pump, a loop filter, and a voltage-controlled delay line (“VCDL”) connected in series. The input reference signal can be fed to one input of the PD. An output of the VCDL can also be fed back to a second input of the PD. If the phase of the feedback clock signal is not locked to that of the reference signal, then the PD can output a voltage signal whose magnitude is indicative of the amount of the phase difference. That signal can be filtered by the charge pump and loop filter and input to the VCDL, thereby altering its phase delay. Eventually, the phase of the output clock signal can lock to the phase of the reference signal. Unlike PLLs, DLLs generally do not affect the frequency of the signal; the output frequency will automatically match the input frequency.
In some cases, a PLL can support the use of both a PD and a PFD. For instance, a PLL might be used to perform clock data recovery (“CDR”) using a PD, and to generate a transmission clock signal using a PFD. In such cases, the PLL can also include two loop filters, one for use with the PD and one for use with the PFD. The two loop filters can be designed to match the individual bandwidth requirements associated with the PD or the PFD. Unfortunately, utilizing multiple loop filters in a single PLL can consume a relatively large amount of area and impose relatively difficult design requirements.
In view of the foregoing, it would be desirable to provide methods and apparatus for varying the bandwidth of a single loop filter in a loop circuit. In addition, it would be desirable to provide such methods and apparatus while consuming a relatively small amount of area.